Modern day complex system-on-chip (SOC) architectures contain multiple processor cores. In one example, the architecture incorporates two processor cores—a digital signal processor (DSP) and a microprocessor—and a shared memory, in addition to other components.
To improve performance and flexibility, access by the DSP to the shared memory is mapped by a memory management unit (MMU) inside a subsystem of the DSP. The DSP MMU not only maps physical memory into the virtual address space of the DSP, but also traps any access made to an unmapped region. Access by the DSP to unmapped memory results in a fault also referred to as a page fault or a memory management fault, whereupon the DSP can stall.
Faults resulting from an invalid virtual address by the DSP can be difficult to debug. Memory management faults typically result in the DSP crashing silently, rendering it incommunicado from any external sub-system. Even with hardware debuggers, these types of faults are difficult to catch because there is no predictable place to put a breakpoint. Further exacerbating the problem is that sometimes such faults occur very infrequently and may depend upon unique conditions such as background noise.
Therefore, to address the above described problems and other problems, what is needed is for a memory management fault caused by one of the multiple processors to be handled gracefully, for example to produce useful information that can be used to narrow down or debug problematic code.